Data interconnect links are used for signaling between different components of a chip, such as processors and memory controllers. Multi-processor systems often include a data interconnect fabric including many data interconnect links and routers. Data interconnect fabrics often provide for components to be addressable within the fabric, and employ packet-based communications to improve efficiency. However, such systems frequently suffer from communications delay due to communication buffer overflows and data traffic congestion.
One existing solution to such problems is to use an on-off signaling in which an “off” signal applies back pressure to stop transmission of more packets of flits (flow control units) when the number of buffers drops below a threshold. However, such solutions often suffer from excessive latency due to waiting for on-off signaling.
Another existing solution is to use a credit-based mechanism in which one end of a link sends flow control credits to the other end, which allow packets or flits to be transmitted. Flow control credits are useful where the width of packets/flits stay constant over the course of transmission from original source to destination.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.